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IS27HC010
IS27HC010
131,072 x 8 HIGH-SPEED CMOS EPROM
ISSI
JULY 1997
ISSI
(R)
(R)
FEATURES
* Fast read access time: 30 ns * Pin compatible with the IS27C010 * High-speed write programming -- Typically less than 30 seconds * Industrial and commercial temperature ranges available * 10% power supply tolerance * JEDEC-approved pinout * Standard 32-pin DIP, PLCC, and TSOP packages
DESCRIPTION The ISSI IS27HC010 is an ultra-high-speed 1 megabit (128Kword by 8-bit) Ultraviolet Erasable CMOS Programmable Read-Only Memory. It utilizes the standard JEDEC pinout making it functionally compatible with the IS27C010, but with significantly faster access capability. This superior random access capability results from a focused high-speed design. This offers users bipolar speeds with higher density, lower cost, and proven reliability. The device is ideal for use with the faster processors. Designers may take full advantage of high-speed digital signal processors and microprocessors by allowing code to be executed at full speed directly out of EPROM. Typical applications include laser printers, switching networks, graphics, workstations, high-speed modems, and digital signal processing. The IS27HC010 uses ISSI's write programming algorithm which allows the entire chip to be programmed in typically less than 30 seconds. This product is available inOne-Time Programmable (OTP) PDIP, PLCC, and TSOP packages over commercial and industrial temperature ranges.
FUNCTIONAL BLOCK DIAGRAM
VCC GND VPP DQ0-DQ7
8
OE CE PGM
OUTPUT ENABLE CHIP ENABLE AND PROG LOGIC
OUTPUT BUFFERS
Y DECODER A0-A16
Y GATING
17
X DECODER
1,048,576-BIT CELL MATRIX
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 1997, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
EP009-1F 07/18/97
1
IS27HC010
PIN CONFIGURATIONS
32-Pin DIP
VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC PGM (P) NC A14 A13 A8 A9 A11 OE (G) A10 CE (E) DQ7 DQ6 DQ5 DQ4 DQ3
ISSI
PIN DESCRIPTIONS
A0-A16 Address Inputs Chip Enable Input Data Inputs/Outputs Output Enable Input Program Enable Input Power Supply Voltage Program Supply Voltage Ground No Internal Connection
(R)
CE (E)
DQ0-DQ7
OE (G) PGM (P)
Vcc VPP GND NC
32-Pin PLCC
PGM (P)
32-Pin TSOP
VCC
VPP
A12
A15
A16
INDEX A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13
NC
4
3
2
1
32
31
30 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE (G) A10 CE (E) DQ7
14
15
16
17
18
19
20
A11 A9 A8 A13 A14 NC PGM (P) VCC VPP A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE (G) A10 CE (E) DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3
DQ1
DQ2
GND
DQ3
DQ4
DQ5
DQ6
2
Integrated Silicon Solution, Inc.
EP009-1F 07/18/97
IS27HC010
FUNCTIONAL DESCRIPTION
Erasing the IS27HC010 In order to clear all locations of their programmed contents, it is necessary to expose the IS27HC010 to an ultraviolet light source. A dosage of 30W - sec/cm2 is required to completely erase the IS27HC010. This dosage can be obtained by exposure to an ultraviolet lamp-wavelength of 2537 Angstroms (A)--with intensity of 12,000 W/cm2 for 30 to 40 minutes. The IS27HC010 should be directly under and about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the IS27HC010, and similar devices, will erase with light sources having wavelengths shorter than 4000A. The exposure to fluorescent light and sunlight will eventually erase the IS27HC010 and exposure to them should be prevented to realize maximum system reliability. If used in such an environment, the package window should be covered by an opaque label or substance. Programming the IS27HC010 Upon delivery, or after each erasure, the IS27HC010 has 1,048,576 bits in the "ONE", or HIGH state. "ZEROs" are loaded into the IS27HC010 through the procedure of programming. The programming mode is entered when 12.75 0.25V is applied to the VPP pin, VCC = 6.25V, CE and PGM is at VIL, and OE is at VIH. For programming, the data to be programmed is applied eight bits in parallel to the data output pins. The write programming algorithm reduces programming time by using 100 s programming pulses followed by a byte verification to determine whether the byte has been successfully programmed. If the data does not verify, an additional pulse is applied for a maximum of 25 pulses. This process is repeated while sequencing through each address of the EPROM. The write programming algorithm programs and verifies at VCC = 6.25V and VPP = 12.75V. After the final address is completed, all byte are compared to the original data with VCC = 5.25V. Program Inhibit Programming of multiple IS27HC010s in parallel with different data is also easily accomplished. Except for CE, all like inputs of the parallel IS27HC010 may be common. A TTL low-level program pulse applied to an IS27HC010 CE input with VPP = 12.75 0.25V, PGM LOW and OE HIGH will program that IS27HC010. A high-level CE input inhibits the other IS27HC010 from being programmed.
ISSI
(R)
Program Verify A verify should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with OE and CE at VIL, PGM at VIH, and VPP between 12.5V and 13.0V. Auto Select Mode The auto select mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25C 5C ambient temperature range that is required when programming the IS27HC010. To activate this mode, the programming equipment must force 12.0 0.5V on address line A9 of the IS27HC010. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during auto select mode. Byte 0 (A0 = VIL) represents the manufacturer code, and byte 1 (A0 = VIH), the device identifier code. For the IS27HC010, these two identifier bytes are given in the Mode Select table. All identifiers manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. Read Mode The IS27HC010 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Output Enable (OE) is the output control and should be used to get data to the output pins, independent of device selection. Data is available at the outputs tOE after the falling edge of OE assuming that CE has been LOW and addresses have been stable for at least tACC - tOE. Standby Mode The IS27HC010 has a standby mode which reduces the maximum VCC active current. It is placed in standby mode when CE is at VIH. The amount of current drawn in standby mode depends on the frequency and the number of address pins switching. The IS27HC010 is specified with 50% of the address lines toggling at 10 MHz. A reduction of the frequency or quantity of address lines toggling will significantly reduce the actual standby current.
Integrated Silicon Solution, Inc.
EP009-1F 07/18/97
3
IS27HC010
Output OR-Tieing To accommodate multiple memory connections, a twoline control function is provided to allow for: 1. Low memory power dissipation, and 2. Assurance that output bus contention will not occur. It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device.
ISSI
(R)
System Applications During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device at a minimum, a 0.1 F ceramic capacitor (high-frequency, low inherent inductance) should be used on each device between VCC and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7 F bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array.
TRUTH TABLE(1,2)
Mode Read Output Disable Standby Program Program Verify Program Inhibit Auto Select(3,5) Manufacturer Code Device Code
CE
VIL VIL VIH VIL VIL VIH VIL VIL
OE
VIL VIH X VIH VIL X VIL VIL
PGM
X X X VIL VIH X X X
A0 X X X X X X VIL VIH
A9 X X X X X X VH VH
VPP VCC VCC VCC VPP VPP VPP VCC VCC
Outputs DOUT Hi-Z Hi-Z DIN DOUT Hi-Z D5H 0EH
Notes: 1. VH = 12.0V 0.5V. 2. X = Either VIH or VIL. 3. A1-A8 = A10-A16 = VIL. 4. See DC Programming Characteristics for VPP voltage during programming. 5. The IS27HC010 can use the same write algorithm during program as other IS27C010 or IS27010 devices.
LOGIC SYMBOL
17 A0-A16 8 DQ0-DQ7 CE (E) PGM (P) OE (G)
4
Integrated Silicon Solution, Inc.
EP009-1F 07/18/97
IS27HC010
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM Parameter Terminal Voltage with Respect to GND All pins except A9 and VPP VPP A9 VCC Ambient Temperature with Power Applied Storage Temperature (OTP) Storage Temperature (All others) Value -0.6 to VCC + 0.5(2) VCC - 0.3 to 13.5(2,3) -0.6 to 13.5(2,3) -0.6 to 7.0(2) -65 to +125 -65 to +125 -65 to +150 Unit V V V V C C C
ISSI
(R)
TA TSTG TSTG
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods less than 10 ns. Maximum DC voltage on output pins is VCC + 0.5V which may overshoot to VCC + 2.0V for periods less than 10 ns. 3. Maximum DC voltage on A9 or VPP may overshoot to +13.5V for periods less than 10 ns.
OPERATING RANGE
Range Commercial Industrial(1) Ambient Temperature 0C to +70C -40C to +85C VCC 5V 10% 5V 10%
Note: 1. Operating ranges define those limits between which the functionally of the device is guaranteed.
DC ELECTRICAL CHARACTERISTICS(1,2,3) (Over Operating Range)
Symbol Parameter VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input Load Current Output Leakage Current
(4)
Test Conditions VCC = Min., IOH = -4 mA VCC = Min., IOL = 12 mA
Min. 2.4 -- 2.0 -0.3
Max. -- 0.45 VCC + 0.5 0.8 5.0 10
Unit V V V V A A
Input LOW Voltage(4) VIN = 0V to +VCC VOUT = 0V to +VCC
-- --
Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. Never try to force VPP LOW to 1V below VCC. Manufacturer suggests to tie VPP and Vcc together during the READ operation. 2. Caution: the IS27HC010 must not be removed from (or inserted into) a socket when VCC or VPP is applied. 3. Minimum DC input voltage is -0.5V. During transitions, the inputs may undershoot to -2.0V for periods less than 10 ns. Maximum DC voltage on output pins is VCC + 0.5V which may overshoot to VCC + 2.0V for periods less than 10 ns. 4. Tested under static DC conditions.
Integrated Silicon Solution, Inc.
EP009-1F 07/18/97
5
IS27HC010
POWER SUPPLY CHARACTERISTICS(1,2,5) (Over Operating Range)
Symbol Parameter ICC1 Vcc Operating Supply Current(3) VPP Current During Read(4) Vcc CMOS Standby Current Vcc TTL Standby Current Test Conditions VCC = Max., CE = VIL IOUT = 0 mA, f = 10 MHz (Open outputs) VCC = Max., CE = OE = VIL VPP = VCC Commercial Industrial Min. -- -- -- -- Max. 75 90 1.0 20
ISSI
Unit mA
(R)
IPP1 ICCSB0
A mA
CE VCC - 0.3V All pins VCC - 0.3V or 0.3V toggling f 10 MHz CE VIH All pins = VIH or VIL (TTL Level) toggling f 10 MHz
ICCSB1
--
35
mA
Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. Never try to force VPP LOW to 1V below VCC. Manufacturer suggests to tie VPP and Vcc together during the READ operation. 2. Caution: the IS27HC010 must not be removed from (or inserted into) a socket when VCC or VPP is applied. 3. ICC1 is tested with OE = VIH to simulate open outputs. 4. Maximum active power usage is the sum of ICC and IPP. 5. Minimum DC input voltage is -0.5V. During transitions, the inputs may undershoot to -2.0V for periods less than 10 ns. Maximum DC voltage on output pins is VCC + 0.5V which may overshoot to VCC + 2.0V for periods less than 10 ns.
CAPACITANCE(1,2,3)
DIP Symbol CIN1 CIN2 CIN3 COUT Parameter Address Input Capacitance Conditions VIN = 0V VIN = 0V VIN = 0V VOUT = 0V Typ. 6 10 10 8 Max. 10 10 10 12 PLCC/TSOP Typ. Max. 6 7 7 6 9 9 9 9 Unit pF pF pF pF
OE Input Capacitance CE Input Capacitance
Output Capacitance
Notes: 1. Typical values are for nominal supply voltage. 2. This parameter is only sampled, but not 100% tested. 3. Test conditions: TA = 25C, f = 1 MHz.
SWITCHING TEST CIRCUIT
Device Under Test CL1 = 30 pF CL2 = 5 pF CL RL = 121 VL = 1.9V
SWITCHING TEST WAVEFORM
3V
OUT
0V
1.5V
TEST POINTS
1.5V
INPUT
OUTPUT
Notes: AC Testing: 1. Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0". 2. Input pulse rise and fall skew rate 1.5V/ns.
6
Integrated Silicon Solution, Inc.
EP009-1F 07/18/97
IS27HC010
SWITCHING CHARACTERISTICS(1,3,4) (Over Operating Range)
JEDEC Symbol Std. Symbol -30 Parameter Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable HIGH or Output Enable HIGH, whichever comes first, to Output Float Output Hold from Address, CE or OE whichever occured first Test Conditions Min. -- -- -- 0 Max. 30 30 10 10 Min. -- -- -- 0 -45 Max. 45 45 20 20 Min. -- -- -- 0 -70 Max. 70 70 35 35
ISSI
Unit ns ns ns ns
(R)
tAVQA tELQV tGLQV tEHOZ, tGHQZ
tACC tCE tOE tDF(2)
CE = OE = VIL
CL = CL1 CL = CL1 CL = CL1
OE = VIL CE = VIL
CL = CL2
tAVOX
tOH
0
--
0
--
0
--
ns
Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. 2. This parameter is only sampled, not 100% tested. 3. Caution: The IS27HC010 must not be removed from (or inserted into) a socket or board when VPP or VCC applied. 4. Output Load: 1 TTL gate and C = CL. Input Rise and Fall times: 2 ns. Input Pulse Levels: 0 to 3V. Timing Measurement Reference Level: 1.5V for inputs and outputs.
SWITCHING WAVEFORMS
3V
ADDRESS
0V
1.5V
ADDRESS VALID
1.5V
CE
tCE
OE
tOE tDF(2) tOH VALID OUTPUT Hi-Z tACC Hi-Z
(1)
OUTPUT
Notes: 1. OE may be delayed up to tACC - tOE after the falling edge of CE without impact on tACC. 2. tDF is specified from OE or CE, whichever occurs first.
Integrated Silicon Solution, Inc.
EP009-1F 07/18/97
7
IS27HC010
DC PROGRAMMING CHARACTERISTICS(1,2,3,4) (TA = +25C 5C)
Symbol Parameter VOH VOL VIH VIL VH ILI ICC IPP VCC VPP Output HIGH Voltage During Verify Output LOW Voltage During Verify Input HIGH Voltage Input LOW Voltage (All Inputs) A9 Auto Select Voltage Input Current (All Inputs) VCC Supply Current (Program & Verify) VPP Supply Current Supply Voltage Programming Voltage VIN = VIL or VIH Test Conditions IOH = -400 A IOL = 2.1 mA Min. 2.4 -- 2.0 -0.3 11.5 -- -- -- 6.0 12.5 Max. -- 0.45 VCC + 0.5 0.8 12.5 10.0 50 30 6.5 13.0
ISSI
Unit V V V V V A mA mA V V
(R)
CE = VIL, OE = VIH
SWITCH PROGRAMMING CHARACTERISTICS(1,2,3,4) (TA = +25C 5C)
JEDEC Symbol Std. Symbol Parameter Address Setup Time Min. 2 2 2 0 2 0 2 95 2 2 -- Max. -- -- -- -- -- 130 -- 105 -- -- 150 Unit s s s s s ns s s s s ns
tAVEL tDZGL tDVEL tGHAX tEHDX tGHQZ tVPS tELEH1 tVCS tELPL tGLQV
tAS tOES tDS tAH tDH tDFP tVPS tPW tVCS tCES tOE
OE Setup Time
Data Setup Time Address Hold Time Data Hold Time
OE HIGH to Output Float Delay
VPP Setup Time
PGM Program Pulse Width
VCC Setup Time
CE Setup Time
Data Valid from OE
Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. 2. VPP must be VCC during the entire programming and verifying procedure. 3. When programming IS27HC010, a 0.1 F capacitor is required across VPP and ground to suppress spurious voltage transients which may damage the device. 4. Programming characteristics are sampled but not 100% tested at worst-case conditions.
8
Integrated Silicon Solution, Inc.
EP009-1F 07/18/97
IS27HC010
PROGRAMMING ALGORITHM WAVEFORM(1,2)
PROGRAM VERIFY
ISSI
(R)
PROGRAM
ADDRESS
tAS tAH DATAIN STABLE tDS
12.75V
DATA
Hi-Z tDH
DATAOUT VALID tDFP
VPP
Vcc-0.3V
tVPS
6.0V-6.5V
VCC
5V10%
tVCS
CE
tCES
PGM OE
tPW tOES
tOE
Max
Notes: 1. The timing reference level is 1.5V for inputs and outputs. 2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer.
Integrated Silicon Solution, Inc.
EP009-1F 07/18/97
9
IS27HC010
PROGRAMMING FLOW CHART
ISSI
(R)
Start
Address = First Location
Vcc = 6.25V VPP = 12.75V
X=0
Interactive programming Section
Program One 100 s Pulse
Increment X
Yes X = 25?
No Fail Verify Byte
Pass Increment Address No Last Address?
Yes Vcc = VPP = 5.25V
Verify Section
Verify All Bytes Pass Device Passed
Fail
Device Failed
10
Integrated Silicon Solution, Inc.
EP009-1F 07/18/97
IS27HC010
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed (ns) 30 Order Part Number IS27HC010-30W IS27HC010-30PL IS27HC010-30T IS27HC010-45W IS27HC010-45PL IS27HC010-45T IS27HC010-70W IS27HC010-70PL IS27HC010-70T Package 600-mil Plastic DIP PLCC - Plastic Leaded Chip Carrier TSOP 600-mil Plastic DIP PLCC - Plastic Leaded Chip Carrier TSOP 600-mil Plastic DIP PLCC - Plastic Leaded Chip Carrier TSOP
ISSI
(R)
45
70
ORDERING INFORMATION Industrial Range: -40C to +85C
Speed (ns) 30 45 70 Order Part Number IS27HC010-30PLI IS27HC010-30TI IS27HC010-45PLI IS27HC010-45TI IS27HC010-70PLI IS27HC010-70TI Package PLCC - Plastic Leaded Chip Carrier TSOP PLCC - Plastic Leaded Chip Carrier TSOP PLCC - Plastic Leaded Chip Carrier TSOP
ISSI
(R)
Integrated Silicon Solution, Inc.
2231 Lawson Lane Santa Clara, CA 95054 Fax: (408) 588-0806 Toll Free: 1-800-379-4774 http://www.issiusa.com
Integrated Silicon Solution, Inc.
EP009-1F 07/18/97
11

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